Bipolar transistors can be formed using a polysilicon self-aligned technique, such as disclosed in a pending U.S. patent application, entitled "A Polysilicon Self-Aligned Bipolar Device and Process of Manufacturing, the Same," filed Nov. 19, 1986, Ser. No. 932,752 now U.S. Pat. No. 4,799,099. The subject matter of which is incorporated herein by reference in its entirety. The polysilicon self-aligned transistors have several advantages over prior art transistors.
In forming polysilicon self-aligned bipolar transistors, a P type polysilicon is deposited over a semiconductor surface. The P type polysilicon is patterned to define an opening for the emitter of the transistor. The polysilicon layer is then etched, stopping on bare silicon. Subsequently, a base is diffused through the opening, and an emitter is formed therein.
This process presents several difficulties. The first difficulty concerns etching the polysilicon layer to stop on the bare silicon. Since there is a lack of selectivity between polysilicon and silicon, etching and stopping on silicon without damage to the substrate is very difficult. The second difficulty concerns the very fine geometries printed and etched in the polysilicon to define the window.
Through photographic techniques, such as image reversal, the difficulty of patterning small holes in the polysilicon layer can be minimized. However, once patterned, the difficulty in etching the small holes is not relieved. One way to circumvent the etching problem is to grow the polysilicon layer at the same time the epitaxy layer is being grown, as reported in F. Mieno, et al., "Novel Selective Poly and Epitaxial Silicon Growth Technique for USLI Processing," IEDM Technical Digest, p. 16-19 (1987). Unfortunately, this process will not lead to a fully self-aligned device.
Therefore, a need has arisen in the industry to provide a self-aligned bipolar transistor which avoids the problems associated with stopping an etch on silicon. Furthermore, the polysilicon self-aligned bipolar transistor should be capable of implementation in small geometries.